1. Field of the Invention
A device and methods are disclosed that provide ultra-thin, stackable wafers and layers incorporating fully tested and functional singulated integrated circuit die or modified integrated circuit packages. This disclosed invention takes advantage of, and advances related approaches to making and assembling ultra-thin, stackable layers such as those disclosed in U.S. Pat. Nos. 5,953,588, 6,072,234, 6,117,704, and 6,195,268, all of which are incorporated herein by reference.
Specifically, the invention relates to methods for creating a “neo-wafer” from previously singulated integrated circuit die or thinned commercial of the shelf (COTS) integrated circuit packages and also relates to a neo-wafer created according to the methods. The invention is suitable for creating neo-wafers for use in wafer-scale integration, manufacturing of multi-chip modules, wafer-scale, three-dimensional packaging, and in processes requiring build up of non-silicon based circuitry on the surface of a previously tested wafer.
2. Description of the Prior Art
Microelectronic packages typically include an integrated circuit die formed on a semiconductor material, which as been bonded to a lead frame and encapsulated in a plastic material. The integrated circuit die themselves are manufactured by creating multiple, individual die on a single, standard geometry semiconductor wafer using well known industry techniques. After manufacturing and testing of the die at the wafer level, the individual die are diced, or singulated, for use in a variety of microelectronic package formats.
There is a need in the industry to recreate “neo-wafers” from die that have previously been singulated from the original semiconductor wafer or from modified COTS microelectronic packages. Applications for neo-wafers include uses in wafer-scale integration, manufacturing of multi-chip modules, wafer-scale, three-dimensional packaging, and in processes requiring build up of non-silicon based circuitry on the surface of a previously tested wafer.
In the case of wafer-scale integration, there is a requirement that the wafer contain only tested and fully functional die and that no failed die exist on the wafer. Present wafer manufacturing techniques make 100% die yield on a single wafer generally unattainable.
In the field of multi-chip module manufacturing, the object of the invention is to provide a neo-wafer with a heterogeneous mix of die, potentially manufactured using different processes and foundries.
Neo-wafers incorporating heterogeneous or homogeneous die are also beneficially used in wafer-scale, three-dimensional packaging where wafers containing integrated circuit die are stacked, diced and the individual layers interconnected to form high-density electronic modules. In such applications, 100% die yields are desirable on each wafer in the stack to ensure a failed individual die does not result in making the entire stacked module in which it is incorporated useless.
Finally, the process of non-silicon circuit build up necessitates the reassembly of fully functional individual die into a wafer so that wafer level processes, such as deposition, lithography, and doping, can be performed on the surface of the rewafered die.
Unfortunately, it is presently difficult to create neo-wafers, particularly because of the problem of integrated circuit die alignment on the neo-wafer. It is desirable that the die incorporated into the neo-wafer be aligned and oriented with the same degree of accuracy as found in conventional wafers before die singulation.
It is therefore an object of the disclosed invention to address the die alignment problem while creating a neo-wafer that is compatible with industry standard wafer level processes that can be handled and processed in the same manner as a standard, non-singulated, semiconductor wafer.